The present invention generally relates to microcomputing devices such as microprocessors, microcontrollers, digital signal processors (DSP), or reduced instruction set computers (RISC). More particularly, this invention relates to an apparatus and method for performing real-time data exchange with a microcomputing device for monitoring and debugging such devices and application programs intended for such devices.
Microcomputing devices of the past, because of their architecture and slower speed, were typically constrained to one or two concurrent tasks. A foreground task consumed the lion""s share of the device""s processing capacity, while background tasks were performed aperiodically by way of interrupts. Existing methods of debugging both foreground and background tasks on microcomputing devices include data exchange via stop-mode emulation using hardware and software breakpoints, and real-time data exchange via interrupts and a serial interface.
Using stop-mode emulation, when a breakpoint is encountered in either a foreground or background task, the device core (and hence processing on all types of tasks) comes to a halt. This method of emulation and debug can be fatal to some application hardware, especially when monitoring and debugging software applications for hardware such as hard disk drives, weapons guidance control systems, or any systems involving feedback control of electric motors or gas engines. For example, a breakpoint may occur while the hard disk drive spindle is spinning and the drive heads are extended and airborne. If the process (typically a background process) that controls spindle speed is halted, the spindle may slow down causing the heads to lose lift and crash into the platters.
While processing of foreground and background tasks is halted, the registers, memory, and input/output (I/O) of the microcomputing device may be examined and modified, and tasks may be advanced one instruction at a time, i.e., single-stepped. Particularly in the case of U.S. Pat. No. 5,329,471 (""471), the microcomputing device""s core is halted and effectively replaced by separate state machine circuitry that retrieves and modifies registers memory, and I/O. As described in the ""471 patent, all background tasks are typically disabled.
With real-time data exchange via interrupts and a serial interface, it is possible for the microcomputing device to respond to a software breakpoint while allowing background tasks to continue. However, existing implementations of this method require substantial data exchange interrupt service routines that occupy program memory space to implement data exchange functions. These service routines, if not stored in ROM, must be downloaded in to program memory before monitoring and debugging.
The most constraining drawback of existing methods of real-time data exchange is that simple functions such as reading or writing from memory require an unacceptable amount of processing cycles to complete. For example, a typical data exchange command comprises at least four bytes as follows.  less than command greater than ,  less than address high greater than ,  less than address low greater than ,  less than data greater than . When communicated through an eight-bit serial port, the command requires at least four interrupts, one for each byte, to be completely received. Once received, even more processing cycles are required to evaluate and execute the command.
By modifying the architecture of the microcomputing device so that data exchange capabilities are inherent in the device itself, the disadvantages of existing data exchange methods may be overcome so that such commands may be handled without halting foreground or background processes, and with reduced processing overhead. The present invention accomplishes this while continuing to support the use of hardware and software breakpoints, and single-step operation.
The present invention consists of apparatus and methods for data exchange with microcomputing devices. In one embodiment, the invention consists of a microcomputing device having a plurality of instruction buses. The first bus is the primary instruction bus from which the device core receives application instructions. A secondary bus is the bus from which the device core receives data exchange instructions. Operative with the plural instruction buses is circuitry for receiving data exchange instructions on the secondary instruction bus and circuitry for selecting from which of the instruction buses the core fetches instructions on any given cycle. In addition to plural instruction buses, some instructions specific to data exchange have been added to the core""s instruction set. These added instructions allow the device to perform data exchange instructions such as read and write with a single-word data exchange instruction.
The present invention is represented by an eight-bit microcontroller core capable of executing standard Motorola 68HC05 object level instructions in its normal mode, and data exchange instructions during data exchange. The primary instruction bus is 8 bits wide. The secondary instruction bus is 32 bits wide, allowing for the operation code (op code), address (both high and low bytes), and data to be included in one 32-bit instruction enabling a single data exchange instruction fetch cycle. In this implementation, the device core is responsive to 32-bit wide data exchange instructions presented on the secondary instruction bus and executes data exchange read and write operations in only 3 clock cycles. No interrupts, and therefore no lengthy context save and restore operations are required. Hence, the invention requires no separate data exchange code in order to read from or write to memory or I/O.
In the preferred embodiment, the circuit for presenting data exchange instructions to the secondary instruction bus is by way of a Joint Test Advisory Group (JTAG) Institute of Electrical and Electronics Engineers (IEEE) 1149.1 scan path. However, a number of other circuits, such as RS-232 or bond-out parallel I/O, may be used to present data exchange instructions. Once data exchange instruction is presented to the secondary instruction bus, a data exchange request signal is generated. On the next op code fetch cycle, the core will fetch a single 32-bit data exchange instruction from the secondary instruction bus. During the fetch and execution of the data exchange instruction, a signal is provided to indicate that the data exchange cycle is active. When the data exchange cycle is completed, another signal is provided to indicate completion. These signals may be sensed and cleared by external means.
According to another aspect of the present invention, a method for summoning the core to perform a data exchange subroutine without the use of interrupts is provided. In accordance with the method, upon completion of the data exchange subroutine, the device resumes execution of foreground tasks. Appropriate flags, able to be sensed and cleared by external means, are provided to indicate that a data exchange subroutine is in service or completed.
The present invention also includes a method for implementing hardware and software breakpoints. Data exchange instructions are provided that gain control of the core to allow foreground processes to be single-stepped, while allowing background processes to continue. Again, flags are provided to indicate breakpoint status and may be sensed and cleared by external means.